This invention pertains generally to digital LSI circuitry, and in particular to a very high speed 32 bit digital adder.
Because the binary adder is a basic building block of a digital computer, the speed of any digital computer is limited by the speed at which the binary adders in such a computer may be operated. The speed at which a 32 bit adder may be operated is of particular importance in a 32 bit computer. It is known that the carry-out, C.sub.OUT, of a first adder may be used as the carry-in, C.sub.IN, input of a complementary second adder to increase the speed of propagating the carry signal by eliminating the delay associated with an inverter stage. However, in a 32 bit adder wherein an array of 16 double adders is used, speed of operation is primarily limited by the delay involved in generating a C.sub.OUT signal through the blocks of adders because the C.sub.OUT signal from each block cannot be generated until the C.sub.OUT signal of all preceding blocks has been generated. That is to say, according to the prior art, the proper C.sub.OUT signals from each one of the blocks of adders making up a 32 bit adder cannot be generated simultaneously.